IT SEEMS INTELíS new Core i7 chip may be a bit soggy on the translation lookaside buffer (TLB) front, with the firm hinting at a bug in an official Specification Update.
A TLB, found in pretty much all current desktop and server processors, is a CPU cache used by memory management hardware to improve the speed of virtual address translation.
Chipzillaís spec update notes "In rare instances, improper TLB invalidation may result in unpredictable system behavior, such as system hangs or incorrect data". The document goes on to say "Developers of operating systems should take this documentation into account when designing TLB invalidation algorithms. For the processors affected, Intel has provided a recommended update to system and BIOS vendors to incorporate into their BIOS to resolve this issue."
here's the linky.......ok Xman time for u to redo my post Updated
Edited by Nvyseal, 02 December 2008 - 05:45 PM.